UMN's chip design club. From your first line of Verilog to a layout ready for fab, on industry tools.
Almost nobody gets to design a chip as an undergrad. SASi exists so you can.
RTL to signoff, hands-on, nothing skipped.
Cadence, Synopsys, and Siemens on our own 20-node cluster.
Open PDKs and shuttle programs, so clean designs can actually ship.
Teammates who will tell you your timing doesn't close.
Every stage needs people. Pick the one you like.
Describe the hardware in SystemVerilog.
→Prove it does what you claimed it does.
→Map that logic onto real standard cells.
→Floorplan, clock tree, and every wire.
→DRC and LVS clean, ready for a shuttle.
Four equivalent ways to qualify. We care whether you can do the work.
EE 2301 or any equivalent digital logic or HDL course.
HDL, testbenches, FPGA builds, open-source hardware, or research.
A short review with someone on the board.
Open to every UMN student, any major.
Subscribe and it shows up next to your classes.
University ASIC and VLSI clubs working in the open and sharing what they learn.
Shared docs and tooling notes, open analog and digital tutorials, a network-wide Discord, and the ASIC Network Hackathon.
If you hire people who can take a design from RTL to GDSII, this is where they come from.
Shuttle slots and mask costs.
Licenses and cluster hardware.
Keeping our free curriculum current.
Conferences, competitions, and speakers.
Tell us what you'd like to support and we'll send a proposal. In-kind counts too: licenses, PDK access, shuttle slots, hardware.
A CSE Campus Life Program. Gifts go through the UMN Foundation and are tax-deductible; partnerships go through the University.
If you can write a little code and want to know how chips get built, you belong here.