ASIC 101 docs

ASIC 101, a documentation site on digital ASIC design for beginners

ASIC stands for Application Specific Integrated Circuit. This course will walk you through the process of creating and designing your very own first ASIC chip.

This book will provide interactive tutorials, quizzes and exercises for you to complete. For interactive lesson portions, we will mainly reference problems from ASIC tutor. If you are a Stone Arch Silicon Member, there will be small self led deliverables which correspond to onboarding, feel free to follow along if you wish.

About ASIC

So what even is an ASIC chip? Unlike general purpose processors, it is a chip built to do one job. Compared to an FPGA, an ASIC chip cannot be reprogrammed after it ships. The circuit on an ASIC chip is permanent, and wired directly into the silicon. An ASIC is typically much more expensive and time consuming to create compared to an ASIC chip. For many companies, developing their own ASICs requires an upfront cost in the millions! However, with a large market volume, the price per processor is much lower with ASIC chips. ASICs are also capable of being more performant and power efficient due to a low silicon overhead. FPGAs arent perpindicular to ASIC technology however. An engineer can benchmark and test ASIC designs on an FPGA before menufacturing, saving a lot of time and money in the case of an error.

There are three main components of digital design covered in this book.

  1. Register Transfer Level (RTL) design:

    The RTL portion involves translating high level design requirements into a cycle-accurate digital representation. Engineers use Hardare Description Languages (HDLs), to define the logic of a system. The RTL description is the foundational source code for all downstream processes. In this book you will learn how to write verilog HDL.

  2. Functional verification:

    Verification is the most time intensive and important steps of ASIC design. Verification is dedicated to proving that the RTL implementation strictly adheres to the behavioral specification of the chip. Its really important to get this stage right. Nobody wants to waste all their time and money manufacturing a broken chip! In this portion of the book, you will learn how to verify your designs using open source tools.

  3. Place and Route (PNR) / Physical Design:

    Placement and routing tools transform the verified RTL code into a physical silicon layout composed of layer drawings and polygons. In this portion of the book, you will learn how design the physical mosfets and metal interconnects on your chip.

Preresiquite Content

This book assumes prior knowledge on boolean logic design, roughly to the same level of EE2301 from the University of Minnesota.

Additionally:

  • A linux shell you're comfortable in (wsl is ok)
  • Git, and a GitHub account. (Github will be used for submitting SASi deliverables)

Instructions for setting up most of the build environment tools used in this book can be found online if not in the appendix or chapter content.

Words from the authors

ASIC design can be a challenging topic to dive headfirst into. If you are having serious issues, don't be afraid to ask a senior member of your club for help. We were all once beginners, just like your. The most important thing to do when reading this book is to have fun. Learning is fun. Have Fun! - Bear BlinSchauer