Quick Start Tutorial
A self-paced project that walks the entire chip-design flow twice: once fast, on an FPGA, so you have a working design in days instead of weeks; then again for real, through an open-source ASIC flow that ends in a GDSII layout. Both halves build the same 8-bit ALU, so the second half is about the physical-design process, not re-learning the RTL.
Part 1 — Build an 8-bit ALU (FPGA, Vivado)
Specify, write, and verify an 8-bit ALU, then synthesize and implement it in Vivado. You pick one of three adder architectures to build the ALU around:
| Adder | Difficulty |
|---|---|
| Ripple Carry | Beginner |
| Carry Lookahead | Intermediate |
| Carry Select | Intermediate |
Everyone verifies, synthesizes, and implements the same way regardless of which adder they chose, then closes out the part by reading Vivado's timing, utilization, and power reports and writing up what they mean.
Part 2 — RTL to GDSII (open-source ASIC flow)
Take the same verified ALU through an open-source standard-cell flow: install the toolchain, synthesize into real standard cells, floorplan, build a power grid, place, route the clock tree and signal nets, extract parasitics, run static timing analysis, and clear signoff checks (DRC, LVS, antenna, XOR). The part ends with a GDSII layout and a tapeout-readiness checklist.
Prerequisites
- A Linux shell you're comfortable in (WSL is fine)
- Git, and a GitHub account for turning in work
- Verilog at the level of EE 2301 — modules, always blocks, testbenches
Start here
Begin with What an ASIC is, which covers what you'll need before lesson 2 and gets blink, a trivial first module, simulating.